Reduce inverter power

How to reduce short-circuit current and dynamic power consumption of CMOS inverter?

Therefore, the purpose of this work is to reduce short-circuit current and dynamic power consumption of the CMOS inverter. For this purpose, it is proposed to limit the short-circuit current by changing the state of additional PMOS and NMOS transistors included in the path of the short-circuit current.

Can CMOS inverters reduce power consumption?

The prob-lem of reducing power consumption is especially relevant in microprocessors, high-speed ICs, wearable devices, and devices with powerful output bufers. Therefore, in digital circuits, reducing the power con-sumption of CMOS inverters is an actual problem.

How to calculate total power consumption of CMOS inverter?

Total Power Consumption of CMOS Inverter : Now, by considering all the power dissipation components i.e. dynamic power dissipation, power dissipation in direct current paths and static power dissipation, the total power dissipation is given by, Ptotal = Pdynamic + Pdp + Pstatic = CL VDD2 f + tdp * VDD * Ip * f + Ileakage VDD

How to limit leakage current in CMOS inverter?

The transistors alternately switch to the of state, thereby limiting the leakage current in the CMOS inverter. This technique of limiting leakage current is known as the LECTOR approach. A known modification of approach LECTOR in which tran-sistors of pull up and pull down network are replaced by two half sized transistors (Kumar 2013).